I designed a nibble-oriented CPU in Verilog to build a scientific calculator
Summary
The article presents a project that implements a nibble-oriented CPU in Verilog for an FPGA-based scientific calculator, including a soft CPU, microcode firmware, and verification tools. It details project structure, required tools, and build steps, highlighting an open-source hardware approach and online demos. The content is valuable for hardware designers and SMBs exploring FPGA-based prototyping.