Microcode inside the Intel 8087 floating-point chip: register exchange
Summary
This article delves into the microcode inside Intel's 8087 floating-point co-processor, focusing on how the FXCH instruction exchanges stack registers using a 14-instruction microcode sequence. It explains the microcode structure, the register/tag architecture, and the interaction with hardware during exceptions and masked operations, as well as how the microcode was reverse-engineered from ROM images. The piece also covers how the ROM is extracted and transformed into a readable microcode data table, with acknowledgments to the Opcode Collective and related GitHub resources.