The Return of Rigorous Full-System Timing Simulation
Summary
The article discusses the return of rigorous full-system timing simulation in computer architecture, arguing that the timing simulation wall can be overcome by measuring the right execution intervals and using robust metrics. It contrasts timing vs functional simulation, reviews measurement methods such as phase-based sampling and statistical sampling, and describes a modern framework using QFlex for ARM ISA. It also outlines critical challenges like accurate state generation, checkpointing, and multi-node scalability.