STEPLA-1 8-bit Hardwired CPU
Summary
STEPLA-1 is an 8-bit Harvard architecture CPU built from discrete logic gates, designed and simulated in Logisim-Evolution. The project emphasizes full transparency with a hardwired control unit, gate-level signal tracing, and extensive documentation, including an ISA, boot protocol, and a roadmap for future features. The repository highlights an educational, open-source approach to hardware design and manual-level CPU construction.