From GAA to 3D Stacked FET: Expanding the Transistor into the Third Dimension
Summary
Samsung Electronics’ Semiconductor Research Center presents a demonstration of 3D stacked FETs with triple nanosheet channels at a 42 nm gate pitch, highlighting how vertical stacking and gate-all-around (GAA) architecture can boost density and drive current. The article covers the challenges of current paths, uniform crystal growth, and isolation (MDI), and explains how these advances position 3D stacked FETs as a practical evolution of GAA for future logic technologies, backed by visuals and test results from the VLSI Symposium.