IBM Debuts World’s First Sub-1 Nanometer Chip Technology
Summary
IBM announced the world’s first sub-1 nanometer chip using a 3D nanostack transistor architecture at 0.7 nm. The chip packs nearly 100 billion transistors on a fingernail-sized die, reportedly delivering up to 50% higher performance or 70% greater energy efficiency than the 2 nm node, with production potential within five years. The release also references related research, High NA EUV tooling, and plans for semiconductor leadership initiatives like Anderon for quantum wafers.