Fleet: Hierarchical Task-Based Abstraction for Megakernels on Multi-Die GPUs
Summary
arXiv paper proposing Fleet: a hierarchical task-based abstraction for megakernels on multi-die GPUs. It argues that current flat CUDA/HIP models fail to capture chiplet-level locality, leading to memory traffic inefficiency, and presents a multi-level task model with Chiplet-tasks and per-chiplet scheduling. It reports performance gains on AMD Instinct MI350 with Qwen3-8B for certain batch sizes and discusses energy efficiency and data-center implications.