ECC and DDR5
Summary
The post explores ECC RAM and DDR5, detailing how error-correcting codes (like Hamming) work, the differences between RDIMM and UDIMM, and the concept of Chipkill. It examines DDR5's on-die ECC and the EC4/EC8 variants, argues that on-die ECC is a mitigation rather than a substitute for full ECC, and advocates wider adoption of ECC memory. The piece also discusses real-world reliability concerns, server compatibility, and societal/policy angles for improving data integrity.