Designing an Ethernet Switch ASIC
Summary
Open-source hardware piece detailing the design of a 3-port, 100 Mbps Ethernet switch ASIC. It covers RMII interface to LAN8720A PHYs, pin constraints, on-chip memory vs. store-and-forward tradeoffs, and address-resolution TTL-based aging, with reflections on bring-up, testing, and future directions.