Why aren't my two Cortex-A9 cores cache coherent?
Summary
The article documents debugging an SMP cache coherence problem on a Terasic DE0-Nano-SOC using Cortex-A9 cores. It covers MMU setup, cache enabling, and SCU interaction, detailing why L1/L2 caches may not remain coherent between cores and sharing practical code snippets. The post invites reader feedback and references Rust-based approaches for low-level embedded development.