Memory ordering in CPUs
Summary
The article explains memory ordering in CPUs, contrasting strongly ordered architectures (like x86) with weakly ordered ones (like ARM/RISC-V). It argues that CPUs generally do not strictly follow memory models for every access but use optimistic ordering with post-hoc checks, and contention drives retries. Practical guidance emphasizes reducing contention and understanding memory ordering primarily under contention, with empirical notes on modern multi-core servers.