Reverse Engineering a Chip (or well, a GDS)
Summary
A detailed write-up on reverse-engineering Jane Street's ASIC puzzle from a GDSII layout. It describes extracting and tracing netlists with open-source tools (Yosys, KLayout, SKY130 PDK), converting GDS to Verilog, and analyzing box-level blocks to reveal a 121-bit input, 22-ones solution with a 2D stencil constraint. The post discusses challenges, AI-assisted steps, and a DFS solver to assemble a full solution.