Retrospectively Reverse-Engineering Apple's Neural Engine
Summary
A detailed technical reverse-engineering of Apple's Neural Engine (ANE) focusing on the M1/M5 architecture, including compute cores, the scheduler, memory hierarchy, and the DMA/TD-based control flow. The article explains that ANE operates as a fixed-function dataflow engine configured via task descriptors rather than running an ISA, and discusses implications for transformer workloads and DRAM bandwidth utilization.