When ldaxr Doesn't Work: Exclusive Accesses and Cacheability on AArch64
Summary
A technical deep-dive into implementing a spin lock on AArch64, focusing on exclusive accesses (ldaxr/stxr), memory types and attributes, cacheability (MAIR, SCTLR.C), and the differences between QEMU and real hardware (Raspberry Pi 5). The author analyzes a Data Abort caused by ldaxr on real hardware and demonstrates how enabling write-back cacheability resolves the issue, with a detailed exploration of exclusive monitors and memory ordering.