Making SIMD Code Scale to Any Vector Width
Summary
This post explains how to scale SIMD computation beyond 4-wide vectors by organizing data into lanes and using vector extensions to perform multiple dot products in parallel. It starts with vec3/vec4 examples, extends to 8-lane implementations via AVX2 and SSE, and then applies the approach to a frustum culler with substantial speedups, emphasizing data layout and precomputation. The result is a practical guide to achieving performance gains by transforming memory layouts to align with SIMD lanes.