The DRAM interface and the PHY (why a DDR3+ interface must be tuned at boot)
Summary
This article explains the DRAM interface between an FPGA and DRAM, focusing on why a DDR3+ interface must be tuned at boot. It covers signals, topology, DQS/DQ timing, fly-by routing, write/read leveling, termination, reference voltages, clocks, and the DFI between controller and PHY, with references to LiteDRAM’s BIOS and PHY settings.